In the field of very large scale integration (VLSI) semiconductor devices, as the number of circuits which can be fabricated on a given chip have increased, the manufacturer has increasingly had difficulty in assuring that the device manufactured actually meets its design specifications. This added difficulty has resulted from the fact that once a device is manufactured, there is no easy way to probe the various circuit points in the device to determine if all the circuits are functioning properly.
In order to overcome this problem, device manufacturers have come up with various test strategies. One approach is to functionally test each device using a known test sequence and to analyze the response of the device under test to the known test sequence. If the response is correct, then the device has passed that particular test and further tests can be conducted.
The functional test approach is reasonably effective for relatively simple devices with relatively few possible responses to a relatively few number of possible inputs. As devices become much more complex, however, functional testing quickly becomes a very lengthy process as the number of possible input stimuli to the device increases. Consequently, functional testing has not proved to be an effective approach for testing VLSI devices.
To overcome this difficulty, various other approaches have been suggested. The level sensitive scan design approach is one which has been utilized by many design teams. In this approach, a scan path is established which allows data to be scanned into internal registers in a device under test. Then, the device is allowed to run for one or more clock cycles. Thereafter, data is scanned out of the device and compared with the data expected as determined by a logic simulator. When the simulator output and the scanned output do not agree, a manufacturing flaw has been detected.
The LSSD design philosophy does have some drawbacks. In the first place, the circuitry required to implement an LSSD design is quite a bit larger in number and size than a comparable design made without compliance with LSSD design rules. In the second place, many circuits, such as flip-flops, are difficult to design and layout in a manner which complies with LSSD design rules. In the third place, circuits which do meet LSSD design rules frequently require a considerably larger number of interconnects which further reduces the actually usable area of a gate array device in which the circuit is included. In the fourth place, typical designs which do comply with LSSD design rules are capacitive thereby slowing the circuit operation.